1. Technical Field
The present invention relates generally to a correction circuit, and more particularly to a clock signal duty correction circuit.
2. Related Art
A conventional clock signal duty correction circuit has employed a method of correcting a duty rate (hereinafter, referred to as a duty) of a clock signal by adjusting a slew rate of rising and falling edges of the clock signal and a method of correcting a duty of a clock signal by varying a delay time using a delay line.
However, the method of adjusting the slew rate incurs a problem that limits a bandwidth of a clock signal and causes jitters.
Furthermore, a method using the delay line increases a circuit area and a transfer delay time due to the delay line, thus increasing a duty correction time.